1. Technical Field
The present invention relates to a test apparatus.
2. Related Art
Conventionally, as a test apparatus that tests devices such as memories, an apparatus is known that tests high-speed devices such as DDR devices, as shown in Patent Document 1, for example. This test apparatus has a normal mode for generating one piece of pattern data for each prescribed test period and a high-speed mode for generating a plurality of pieces of pattern data for each test period.    Patent Document 1: Japanese Patent Application Publication No. 2000-11692
The test apparatus includes a data memory that stores a plurality of predetermined patterns and outputs a designated pattern for each test period. Each pattern in the data memory includes a number of bits corresponding to the number of pieces of pattern data, and therefore a plurality of pieces of pattern data can be generated for each test period.
For example, each pattern may include a first-half bit sequence corresponding to the first half of the test period and a second-half bit sequence corresponding to the second half of the test period. The pattern data for the first half is generated according to the first-half bit sequence, and the pattern data for the second half is generated according to the second-half bit sequence, and therefore the pattern data can be generated at much higher speed. Furthermore, the pattern data can be generated in the normal mode by selecting a pattern that causes the first-half bit sequence and the second-half bit sequence to be the same.
However, there are cases where the number of bits of a designation signal for designating a pattern of the data memory is determined according to the number of patterns to be generated in the normal mode. For example, when a data pattern PAT to be input to the device under test has a binary value of I/O and an expected value pattern EXP to be compared to the output signal from the device under test has 4 values of H/L/Z/H, 6 (2+4) patterns should be able to be generated in the normal mode. In this case, the number of bits of the designation signal is set to 3.
In response to this, in the high-speed mode, there are four types of values for the data pattern PAT in a test period, which are (first-half data, second-half data) values of (0, 0), (1, 0), (0, 1), and (1, 1). In the same manner, the expected value pattern EXP in a test period has 16 (4×4) types of values. Therefore, it is impossible to designate all of the patterns in the high-speed mode using a 3-bit designation signal.
For example, eight pattern can be designated using a 3-bit designation signal, and therefore when the data pattern PAT is allocated to the patterns of four designation signals, only four designation signal patterns can be allocated to the expected value pattern EXP. As a result, it is impossible to designate each high-speed expected value pattern EXP.